Downsizing and drivability enhancement of a MOS transistor are important issues since the MOS transistor is an electronic device locating at the core of electronic technology.
One method to enhance the drivability of a MOS transistor is to make a gate width larger to decrease the on-resistance. However, enlargement of the gate width has a problem that the occupied area by the MOS transistor becomes larger.
Japanese Patent Application Laid-open No. 2006-294645 proposes a technique to make the gate width larger while increase in the occupation area of a MOS transistor having lateral MOS structure is suppressed.
In this technique, as illustrated in a perspective view of FIG. 8A, trench portions 10 are provided in a well 5, and a gate electrode 2 is formed on the upper surface and inside of the trench portions 10 via an insulating film 7.
On a surface of the well 5, a source region 61 is provided on one side of the gate electrode 2 while a drain region 62 is provided on the other side of the gate electrode 2.
FIG. 8B is a sectional view taken along the line A-A in FIG. 8A. As illustrated in FIG. 8B, the length of the edge in contact with the insulating film 7 becomes the gate width because the gate electrode 2 is formed in the trench portions 10.
In this way, according to this technique, by forming a gate portion in the shape of a trench structure having convex portions and concave portions, the effective gate width can be made larger in relation to the length of the gate electrode 2 on the surface, and thus, the on-resistance per unit area can be decreased without lowering the withstanding voltage of the MOS transistor.
However, the structure illustrated in FIG. 8A has a problem in that, as a gate length L becomes smaller, desired drivability becomes more difficult to obtain.
FIG. 8C is a sectional view taken along the line B-B in FIG. 8A. As can be easily understood with reference to FIG. 8B, FIG. 8C is a sectional view taken along a line which is quite close to the side wall of the trench where a channel region 12 is formed. Current flows along a current path 13 in the channel region 12 generated between the source and the drain illustrated in FIG. 8C. The current path 13 is shorter in an upper portion of the channel region 12 than in a lower portion of the channel region 12, and, the shorter the gate length L becomes, the more outstanding the difference becomes. More specifically, the shorter the gate length L becomes, the more intensively current flows along the current path 13 in the upper portion of the channel region 12, and almost no current flows along the current path 13 in the lower portion, and thus, there is a problem that the channel region 12 can not be effectively used and desired drivability can not be obtained.